As I continue to explore the boundaries between computing hardware, firmware and software as part of an effort to reduce the perceived complexity to something that I can understand, the idea arose for a computing platform with an artificially imposed simplicity.
Hackaday has run competitions for the best code application written in fewer that 1024 bytes of code, so this led me to think about what sort of computing machine could be constructed in fewer than 1024, 2-input NAND gates. Memory would not be counted.
It was whilst pondering this when I received a comment to a past blog post from “BigEd” – who is a participant and moderator in the anyCPU forum
As a result of his comment, I visited the anyCPU forum, and this showed that hardware constrained cpus were nothing new.
anyCPU is a spin-off from 6502.org to address the interests of those actively developing new cpu designs using FPGAs. Several of these cpus were designed with influences from the 6502, using the 6502 as a benchmark for the performance of the new designs. This has led to some interesting challenges within the forum – such as to create an 8-bit design with similar or better performance to the 6502, and the “One Page Computing” challenge – which deserves special mention.
“One Page Computing”
The “OPC” project is to create a fully functioning, useful cpu, who’s design can be captured in just 1 page of verilog code – where a page is defined as 66 lines of 132 characters – or the old green and white, fan-fold, tractor feed line-printer paper.
This artificial design constraint, puts some interesting challenges on the design – and in remarkable short time – has led to an interesting evolution of cpu designs – that meet this criteria. With each generation of the design, the instruction set has improved, as has the performance.
The OPC challenge was conceived in mid-April and in barely 4 months the OPC design has gone through 6 major iterations as outlined in this github project This shows that FPGAs can be used to quickly prototype new cpu designs with minimum of expenditure.
The clever folks on the OPC Project now have written an assembler, and there is a C compiler currently being adapted to cater for the OPC6 instruction set. Another enthusiast is porting PLASMA, a high level bytecoded language to the OPC6.
OPC6 was design constrained by the need for it’s verilog description to fit onto 1 page of printer paper – but this has shown that quite sophisticated cpus can be designed from very little resources.
“BigEd” has done a quick port of the OPC6 onto a Lattice ICE40 – merely to look at the resources used:
After packing: IOs 57 / 206 GBs 0 / 8 GB_IOs 0 / 8 LCs 598 / 7680 DFF 106 CARRY 64 CARRY, DFF 0 DFF PASS 57 CARRY PASS 3 BRAMs 2 / 32 WARMBOOTs 0 / 1 PLLs 0 / 2 After placement: PIOs 33 / 206 PLBs 108 / 960 BRAMs 2 / 32
The after placement figures show that the logic has used about 1/8th of the programmable logic blocks (PLBs) and one sixteenth of the available Block RAM, on the 8k Lattice Ice40.
For comparison – a soft core 6502 uses the following:
After placement: PIOs 27 / 206 PLBs 144 / 960 BRAMs 0 / 32
With low cost FPGA boards now available, for as little as £40, supported by an open-source tool chain, there has never been a better time to get started with “One Page Computing”.
The OPC6 is the latest cpu to evolve from the OPC experiment.
It has 16 registers and provides a fairly comprehensive instruction set allowing register to register operations, not dissimilar to the MSP430, but lacking in several of the addressing modes. The conditional predicate bits allow the instruction to be conditionally executed according to the status of the ALU flag bits.
The OPC6 Instruction set is as follows (See https://revaldinho.github.io/opc/ for full size):