Monthly Archives: April 2017

In my exploration of minimal instruction set (MISC) cpus, it is often a worthwhile exercise to define the instruction set and then simulate the behaviour of the cpu in software. This can be done relatively straightforwardly using even a humble … Continue reading →

I have written a lot about SIMPL over the years, but it is my conviction that it has uses as a tool to help bootstrap various novel processors – and to ease the early stages of processor code development.  It’s … Continue reading →

The 1949 EDSAC This information has been taken from the EDSAC explanatory poster produced by Cambridge university.  I have added some of my own notes for clarity. The 1949 Instruction set EDSAC’s instructions in 1949 was very simple and were … Continue reading →

In September 2017, in Hebden Bridge – as part of the Wuthering Bytes Digital Festival, will host the EDSAC Challenge, in which we will attempt to create the 1949 Cambridge EDSAC computer  as a softcore processor using an FPGA programmed using … Continue reading →

James Bowman developed the J1 Forth CPU in 2010 – and presented a paper describing its architecture at Euroforth  that same year.  It’s a stack based processor – capable of executing Forth primitives mostly in a single cycle. It’s also … Continue reading →

As I read more about Forth, and engage with some of the World’s Forth-Thinkers, I get the impression that at some point Forth becomes addictive and productive.  I have yet to reach that level of enlightenment, but my journey continues … Continue reading →